Design-technology co-optimization to push the scaling limits of digital CMOS circuits
Marie Garcia Bardon
IMEC, Belgium

March 21, 2017, 5 p.m.


Digital circuits have followed a constant pace of scaling: every two years, a new technology generation was produced with reduced area, reduced power, increased speed. The reduction of dimensions lead us today to fundamental limits in both fabrication and device physics. To continue this road of improvements and still get the most of CMOS based technologies, numerous disruptive innovations have to be considered at device and fabrication level, but also at circuit level. We will see how both technology and circuit are modelled and co-optimized in an early development phase to downselect the materials, devices, lithography, circuit options that allows to push forward the CMOS scaling roadmap.



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Design-technology co-optimization to push the scaling limits of digital CMOS circuits
Marie Garcia Bardon
IMEC, Belgium

March 21, 2017, 5 p.m.


Digital circuits have followed a constant pace of scaling: every two years, a new technology generation was produced with reduced area, reduced power, increased speed. The reduction of dimensions lead us today to fundamental limits in both fabrication and device physics. To continue this road of improvements and still get the most of CMOS based technologies, numerous disruptive innovations have to be considered at device and fabrication level, but also at circuit level. We will see how both technology and circuit are modelled and co-optimized in an early development phase to downselect the materials, devices, lithography, circuit options that allows to push forward the CMOS scaling roadmap.



Share